1. Field of the Invention
This invention relates to a memory access device for use in a voice synthesizing apparatus, an image processing apparatus, and the like.
2. Description of the Related Art
FIG. 10 shows the address map of, for example, a 32-bit memory cell array 51. Each cell of the array has row and column addresses. In this memory 51, the cells of any row-selected are successively accessed by designating the column addresses of the cells one after another, or the cell of any column selected are successively accessed by designating the row address of the cells one after another.
In this access method, if the memory 51 has defective cells, as is indicated by the hatching in FIG. 10, defective data will be read out from the memory 51 when the row or column address of any of the defective cells is selected. If, for example, each cell column consists of 1024 cells, at most 1024 defective data items may be read out successively. In view of this, the memory 51 can hardly be used in combination with a voice recording/reproducing circuit or an image processing circuit which has an ADM (Adaptive Delta Modulation) system and which therefore can operate in a comparatively reliable manner against defective data.
In order not to read defective data from the memory 51 by the conventional access method, redundancy technique must be applied to the memory 51. In other words, the memory must be equipped with spare memory cells to be designated by spare row and column addresses and elements associated with the spare cells. Defective memory cells, if exist, are replaced with the spare cells. This redundancy technique inevitably results in a large number of circuit elements, and hence a high manufacturing cost of the memory.